The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which an output circuit and a control circuit for controlling the output circuit are provided on a substrates.
In the case where an inductive load such as a motor, a coil, or the like is driven by switching by a drive circuit (a power transistor), back electromotive force is generated immediately after the direction of a drive current for switching the inductive load changes, resulting in decrease in potential of an output terminal of the drive circuit lower than the ground potential. When the potential of an output terminal of a semiconductor device including such a drive circuit becomes lower than the ground potential, a parasitic transistor in the semiconductor device operates. The parasitic transistor is not a transistor actually formed as an active circuit element but a transistor formed unintentionally in the case where an additional semiconductor region is present next to one semiconductor region in a semiconductor device. For example, when N-type regions are adjacent to each other on a P-type semiconductor substrate, a parasitic NPN transistor is formed. In this case, when the potential of one of the N-type regions becomes negative to allow the parasitic NPN transistor to turn ON, the other N-type region serves as a collector of the parasitic NPN transistor to cause a parasitic current to flow.
When the parasitic transistor operates as above, an abnormal parasitic current flows in a part other than the paths for the essential circuit currents in the semiconductor substrate, inviting malfunction of the drive circuit integrated within the semiconductor device.
For tackling the above disadvantages caused by the parasitic transistor, there is a technique disclosed in Japanese Patent Application Laid Open Publication No. 7-135299A, for example. The technique disclosed in this document will be explained with reference to FIG. 9 and FIG. 10.
FIG. 10 is a plan view schematically showing a structure of a semiconductor device in the above document. On the surface of a semiconductor chip 201 shown in FIG. 10, there are provided a large signal section 202 in which a power transistor is formed, a small signal section 203 in which a control circuit for controlling the power transistor is formed, and a dummy island 204 formed between the large signal section 202 and the small signal section 203. The dummy island 204 is connected to an external power source Vcc.
FIG. 9 is a view schematically showing in section the essential part of the semiconductor device shown in FIG. 10. The semiconductor device is a bipolar semiconductor device fabricated in such a manner that an n-type epitaxial layer 205 is formed on a p-type semiconductor substrate 206, the epitaxial layer 205 is divided by forming a p+-type isolation region 207 to form multiple islands, and elements are formed in each island. Reference numeral 208 denotes an n+-type buried layer. An NPN transistor is formed as a power transistor by forming a p-type base region 213 and forming an n+-type emitter region 214 thereon in the surface portion of an island with the island used as a collector. An n+-type region 209a is formed so as to extend from the surface of the epitaxial layer 205 to the n+-type buried layer 208. This n+-type region 209a is connected to an output terminal (OUT).
FIG. 9 also shows a parasitic transistor Q generated in the semiconductor chip 201. The parasitic transistor Q is a lateral transistor using an island (collector) in which the power transistor is formed as an emitter, the semiconductor substrate 206 as a base, and the n+-type region 209b in the dummy island 204 as a collector.
Malfunction that may be caused in the semiconductor device disclosed in the aforementioned document will be explained below with reference to FIG. 9. When the power transistor switches to drive the inductive load such as a motor, a phenomenon occurs in which supply of the current from the output terminal (OUT) to the inductive load is halted. The inductive load has a characteristic that the current therein continues to flow even when the current supply is interrupted. In this connection, the current flows through a path from the semiconductor substrate 206 to the collector of the power transistor and then to the inductive load even after the current supply is halted. At that time, the potential of the output terminal (OUT) becomes negative lower than the ground potential, so that the semiconductor substrate 206 and the collector of the power transistor are forward biased. Accordingly, the forward diode voltage is applied between the base and the emitter of the parasitic transistor Q to allow the parasitic transistor Q to turn ON.
The parasitic transistor Q can be considered as a combination of two parasitic transistors which share the islands (collector) of the power transistor as an emitter, share the semiconductor substrate 206 as a base, and use the n+-type region 209b in the dummy island 204 and the epitaxial layer 205 in the control circuit as the collectors.
The external power source Vcc is connected to the dummy island 204, so that almost all part (i1) of the collector current of the parasitic transistor Q is supplied from the external power source Vcc thereto the dummy island 204. The supply of the parasitic collector current i1 from the external power source Vcc reduces a parasitic collector current i2 of the parasitic transistor Q using the control circuit as a collector, thereby suppressing malfunction of the control circuit. The technique disclosed in the aforementioned document attains reduction in parasitic collector current i2, which influences the control circuit, to 1/10 to 1/20 of that of a device with no dummy island 204.
Further, the aforementioned parasitic preventing method cannot reduce the parasitic current sufficiently, and another method for suppressing the parasitic current in which arrangement of the power transistor is devised has been employed in combination. Specifically, the power source side power transistor in which no parasitic transistor is generated is arranged between the control circuit and a ground side power transistor to minimize the current amplification (hFE) of the parasitic transistor (see the above document).